Please use this identifier to cite or link to this item:
|Title:||Optimization scheme to minimize reference resistance distribution of spin-transfer-torque MRAM|
|Keywords:||Reference cell resistance distribution|
|Source:||Huang, K., Ning, N., Lian, Y. (2014). Optimization scheme to minimize reference resistance distribution of spin-transfer-torque MRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5) : 1179-1182. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2260365|
|Abstract:||Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is an emerging type of nonvolatile memory with compelling advantages in endurability, scalability, speed, and energy consumption. As the process technology shrinks, STT-MRAM has limited sensing margin due to the decrease in supply voltage and increase in process variation. Furthermore, the relatively smaller resistance difference of two states in STT-MRAM poses challenges for its read/write circuit design to maintain an acceptable sensing margin. The proposed reference circuits optimization scheme solves the reference resistance distribution issue to maximize the sensing margin and minimize the read disturbance, with low power consumption. Simulation results show that the optimization scheme is able to significantly improve the read reliability with the presence of one or few cases of reference cell failure, thus it eliminates the requirement of additional circuits for failure detection of reference cell or referencing to neighboring blocks. © 1993-2012 IEEE.|
|Source Title:||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Feb 21, 2018
WEB OF SCIENCETM
checked on Jan 16, 2018
checked on Feb 18, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.