Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.sse.2008.01.010
Title: Multi-layer high-κ interpoly dielectric for floating gate flash memory devices
Authors: Zhang, L.
He, W. 
Chan, D.S.H. 
Cho, B.J. 
Keywords: Barrier structure
Floating gate
High-κ material
Interfacial layer
Interpoly dielectric
Leakage current
Issue Date: Apr-2008
Citation: Zhang, L., He, W., Chan, D.S.H., Cho, B.J. (2008-04). Multi-layer high-κ interpoly dielectric for floating gate flash memory devices. Solid-State Electronics 52 (4) : 564-570. ScholarBank@NUS Repository. https://doi.org/10.1016/j.sse.2008.01.010
Abstract: We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO2 were studied. It is shown that compared with a conventional Al2O3-HfO2-Al2O3 high-low-high barrier structure, the HfO2-Al2O3-HfO2 multilayer IPD stack with a low-high-low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high-κ IPD. © 2008 Elsevier Ltd. All rights reserved.
Source Title: Solid-State Electronics
URI: http://scholarbank.nus.edu.sg/handle/10635/82726
ISSN: 00381101
DOI: 10.1016/j.sse.2008.01.010
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