Please use this identifier to cite or link to this item: https://doi.org/10.1049/el.2012.4535
Title: Junctionless II-gate transistor with indium gallium arsenide channel
Authors: Guo, H.X.
Zhang, X.
Zhu, Z.
Kong, E.Y.J.
Yeo, Y.-C. 
Issue Date: 14-Mar-2013
Citation: Guo, H.X., Zhang, X., Zhu, Z., Kong, E.Y.J., Yeo, Y.-C. (2013-03-14). Junctionless II-gate transistor with indium gallium arsenide channel. Electronics Letters 49 (6) : 414-415. ScholarBank@NUS Repository. https://doi.org/10.1049/el.2012.4535
Abstract: The fabrication and characterisation of a gate-first In 0.7Ga0.3As channel II-gate junctionless transistor by a CMOS-compatible top-down approach is reported for the first time. The structure uses a simple layer structure and process flow. 3D device simulation shows that the ?-gate structure can deplete the channel carriers more effectively compared with planar and tri-gate devices. The fabricated device with 200 nm gate length shows good transfer characteristics with a Ion/Ioff ratio of -104 and subthreshold swing of -210 mV/decade. The results indicate the suitability of the proposed structure for junctionless transistor operation. © The Institution of Engineering and Technology 2013.
Source Title: Electronics Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/82595
ISSN: 00135194
DOI: 10.1049/el.2012.4535
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