Please use this identifier to cite or link to this item:
|Title:||Integration of high-κ dielectrics and metal gate on gate-all-around si-nanowire-based architecture for high-speed nonvolatile charge-trapping memory|
|Citation:||Fu, J., Singh, N., Zhu, C., Lo, G.-Q., Kwong, D.-L. (2009). Integration of high-κ dielectrics and metal gate on gate-all-around si-nanowire-based architecture for high-speed nonvolatile charge-trapping memory. IEEE Electron Device Letters 30 (6) : 662-664. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2009.2019254|
|Abstract:||This letter, for the first time, presents a metal high-κhigh-κ-oxide silicon-type charge-trapping nonvolatile memory fabricated on an advanced gate-all-around nanowire architecture with a top-down process. The high-κ materials are integrated with a high work-function TaN gate electrode. The fabricated Si nanowire TaN/ Al2O3/HfO2/SiO2/Si (TAHOS) memory can achieve a higher speed at a lower voltage compared with a similar wire-based SONOS device. For instance, at a 13-V programming pulse, the TAHOS memory device resulted in a Vth shift of 3.8 V in 10 μs, while the SONOS took a period of 1 ms to produce a similar shift. Faster program-and-erase speed, particularly the much improved erasing speed in the TAHOS device, could be ascribed to the enhanced electric-field drop in the tunnel oxide in addition to the suppressed gate-electron injection. In addition, good memory-reliability properties could also be observed in the nanowire TAHOS charge-trapping memory. © 2009 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Nov 11, 2018
WEB OF SCIENCETM
checked on Oct 17, 2018
checked on Oct 5, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.