Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2012.2186577
Title: Graphene nanoribbon tunneling field-effect transistors with a semiconducting and a semimetallic heterojunction channel
Authors: Da, H. 
Lam, K.-T.
Samudra, G. 
Chin, S.-K.
Liang, G. 
Keywords: Graphene
heterojunction
tunneling transistors
Issue Date: May-2012
Citation: Da, H., Lam, K.-T., Samudra, G., Chin, S.-K., Liang, G. (2012-05). Graphene nanoribbon tunneling field-effect transistors with a semiconducting and a semimetallic heterojunction channel. IEEE Transactions on Electron Devices 59 (5) : 1454-1461. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2012.2186577
Abstract: We present a computational study of the device performance of graphene nanoribbon tunneling field-effect transistors (TFETs) with a heterogeneous channel. By varying the length and the energy bandgap (Egeneous region, the on- and off-state currents (I ON and $I OFF) can be effectively optimized independently. Both semiconducting and semimetallic heterogeneous regions are studied to understand the effects of $E G engineering on device behaviors. In addition, the effect of gate coverage (GC) over the heterogeneous region is also investigated. We found that device performance is greatly affected by the positioning of the gate to modify the region where band-to-band tunneling occurs. For a given ION/I OFF of eight orders, our results show that, for the semiconducting heterojunction, a higher $I ON can be obtained by having the gate partially covering the heterogeneous region. This is due to a combination of a short tunneling length and resonant states, which leads to an increase in carrier concentration for the tunneling mechanism. On the other hand, for the semimetallic case, a similar $ION/I OFF is only attainable when the heterogeneous region is not covered by the gate. A large $I OFF is observed for even small GC due to the valence electrons from the source traveling to the conduction bands of the semimetallic region, enhancing the carrier transport toward the drain. Our study highlights the device design consideration required when optimizing the device performance of heterojunction TFETs. © 2012 IEEE.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/82425
ISSN: 00189383
DOI: 10.1109/TED.2012.2186577
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