Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2008.922548
Title: Ge-rich (70%) SiGe nanowire MOSFET fabricated using pattern-dependent Ge-condensation technique
Authors: Jiang, Y.
Singh, N.
Liow, T.Y.
Loh, W.Y.
Balakumar, S.
Hoe, K.M.
Tung, C.H.
Bliznetsov, V.
Rustagi, S.C.
Lo, G.Q.
Chan, D.S.H. 
Kwong, D.L.
Keywords: Ge condensation
Heterostructure
SiGe nanowires (SGNWs)
Issue Date: Jun-2008
Source: Jiang, Y., Singh, N., Liow, T.Y., Loh, W.Y., Balakumar, S., Hoe, K.M., Tung, C.H., Bliznetsov, V., Rustagi, S.C., Lo, G.Q., Chan, D.S.H., Kwong, D.L. (2008-06). Ge-rich (70%) SiGe nanowire MOSFET fabricated using pattern-dependent Ge-condensation technique. IEEE Electron Device Letters 29 (6) : 595-598. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2008.922548
Abstract: A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain Si0.7 Ge0.3 to channel Si0.3Ge0.7 regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5× enhancement in the drive current and transconductance Gm as compared to the homojunction planar device Si0.3Ge0.7. This large enhancement can be attributed to several factors including Ωgated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel). © 2008 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/82409
ISSN: 07413106
DOI: 10.1109/LED.2008.922548
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