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|Title:||Enhancing leakage suppression in carbon-rich silicon junctions|
End of range (EOR)
Solid-phase epitaxial (SPE)
|Citation:||Tan, C.F., Chor, E.F., Lee, H., Quek, E., Chan, L. (2006-06). Enhancing leakage suppression in carbon-rich silicon junctions. IEEE Electron Device Letters 27 (6) : 442-444. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2006.874127|
|Abstract:||Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of ∼50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 °C (much lower than typical annealing temperature > 1000 °C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4 × 10-13 A/μm which is much lower than that of 1050 °C spike annealed Si junctions and well within the Ioff requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 μm exhibit an Ioff reduction of ∼10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec. © 2006 IEEE.|
|Source Title:||IEEE Electron Device Letters|
|Appears in Collections:||Staff Publications|
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