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|Title:||Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3 N4 tunneling layer|
|Keywords:||Dual tunneling layer (DTL)|
High-k trapping layer
|Citation:||Wang, Y.Q., Hwang, W.S., Zhang, G., Samudra, G., Yeo, Y.-C., Yoo, W.J. (2007-10). Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3 N4 tunneling layer. IEEE Transactions on Electron Devices 54 (10) : 2699-2705. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2007.904396|
|Abstract:||A novel device structure with a high-k HfO2 charge storage layer and dual tunneling layer (DTL) (SiO2/Si3 N4) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming Vth throughout the cyclic test as compared with SONOS Flash memory devices using an Si3N4 trapping layer. © 2007 IEEE.|
|Source Title:||IEEE Transactions on Electron Devices|
|Appears in Collections:||Staff Publications|
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