Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2007.904396
Title: Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3 N4 tunneling layer
Authors: Wang, Y.Q.
Hwang, W.S.
Zhang, G.
Samudra, G. 
Yeo, Y.-C. 
Yoo, W.J.
Keywords: Dual tunneling layer (DTL)
Endurance
High-k trapping layer
Program/erase speed
Retention
Issue Date: Oct-2007
Citation: Wang, Y.Q., Hwang, W.S., Zhang, G., Samudra, G., Yeo, Y.-C., Yoo, W.J. (2007-10). Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3 N4 tunneling layer. IEEE Transactions on Electron Devices 54 (10) : 2699-2705. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2007.904396
Abstract: A novel device structure with a high-k HfO2 charge storage layer and dual tunneling layer (DTL) (SiO2/Si3 N4) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming Vth throughout the cyclic test as compared with SONOS Flash memory devices using an Si3N4 trapping layer. © 2007 IEEE.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/82246
ISSN: 00189383
DOI: 10.1109/TED.2007.904396
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

38
checked on Jul 11, 2018

WEB OF SCIENCETM
Citations

33
checked on Jul 3, 2018

Page view(s)

16
checked on May 4, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.