Please use this identifier to cite or link to this item:
|Title:||Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancement|
Strain transfer layer
|Citation:||Wang, G.H., Toh, E.-H., Tung, C.-H., Tripathy, S., Samudra, G.S., Yeo, Y.-C. (2008-04-25). Concept of strain-transfer-layer and integration with graded silicon-germanium source/drain stressors for p-type field effect transistor performance enhancement. Japanese Journal of Applied Physics 47 (4 PART 2) : 2551-2555. ScholarBank@NUS Repository. https://doi.org/10.1143/JJAP.47.2551|
|Abstract:||We report a novel strained Si0.75Ge0.25 channel p-type field effect transistor (p-FET) that employs a silicon strain-transfer-layer (STL) buried beneath the channel. At the vertical heterojunction, the compliant silicon strain-transfer-layer, improves the coupling of lattice interactions between the lattice-mismatched SiGe source/drain (S/D) stressors and the channel region. In addition, the lattice interaction between the adjacent S/D stressors and the Si0.75Ge 0.25 channel induces, yet another source of compressive strain in the channel region. A large lateral compressive strain is obtained in the Si 0.75Ge0.25 channel region for hole mobility enhancement. Devices with gate length LG down to 50 nm were fabricated. The strain effects resulted in 84% drive current improvement over unstrained Si channel devices. © 2008 The Japan Society of Applied Physics.|
|Source Title:||Japanese Journal of Applied Physics|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
WEB OF SCIENCETM
checked on Jun 5, 2018
checked on Jun 8, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.