Please use this identifier to cite or link to this item: https://doi.org/10.1088/1674-4926/30/7/074008
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dc.titleBoundary condition and initial value effects in the reaction-diffusion model of interface trap generation/recovery
dc.contributor.authorLuo, Y.
dc.contributor.authorHuang, D.
dc.contributor.authorLiu, W.
dc.contributor.authorLi, M.
dc.date.accessioned2014-10-07T04:24:27Z
dc.date.available2014-10-07T04:24:27Z
dc.date.issued2009
dc.identifier.citationLuo, Y., Huang, D., Liu, W., Li, M. (2009). Boundary condition and initial value effects in the reaction-diffusion model of interface trap generation/recovery. Journal of Semiconductors 30 (7) : -. ScholarBank@NUS Repository. https://doi.org/10.1088/1674-4926/30/7/074008
dc.identifier.issn16744926
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82020
dc.description.abstractA simple standard reaction-diffusion (RD) model assumes an infinite oxide thickness and a zero initial interface trap density, which is not the case in real MOS devices. In this paper, we numerically solve the RD model by taking into account the finite oxide thickness and an initial trap density. The results show that trap generation/passivation as a function of stress/recovery time is strongly affected by the condition of the gate-oxide/poly-Si boundary. When an absorbent boundary is considered, the RD model is more consistent with the measured interface-trap data from CMOS devices under bias temperature stress. The results also show that non-negligible initial traps should affect the power index n when a power law of the trap generation with the stress time, t n, is observed in the diffusion limited region of the RD model. © 2009 Chinese Institute of Electronics.
dc.sourceScopus
dc.subjectCharge pumping
dc.subjectDirect-current current-voltage
dc.subjectInterface-trap generation/passivation
dc.subjectNegative bias temperature instability
dc.subjectReaction-diffusion model
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1088/1674-4926/30/7/074008
dc.description.sourcetitleJournal of Semiconductors
dc.description.volume30
dc.description.issue7
dc.description.page-
dc.identifier.isiut000214934900016
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