Please use this identifier to cite or link to this item:
|Title:||Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices|
|Authors:||Samudra, G. |
|Source:||Samudra, G.,Rajendran, K. (2000-05). Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices. International Journal of Electronics 87 (5) : 513-530. ScholarBank@NUS Repository.|
|Abstract:||Comparative analysis of the minimum surface potential (Φm) and the respective position (or location of barrier peaks (y0)) in various Si MOSFET devices including bulk Si MOSFETs, silicon-on-insulator (SOI) MOSFETs and double-gate SOI MOSFETs has been investigated. For all these three devices we use the same methodology and models to find Φm and y0. The analytical results from the three models are utilized to compare and analyse performance of the related devices. The effects of three main important parameters affecting the Φm and y0, namely channel length (or Lg), drain bias (Vd) and gate bias (Vg), are discussed The main motivation of this paper is to show by comparing the model results how the performance of each device is affected by various changes in physical and electrical parameters. These issues have been elaborately investigated in this work. The short-channel effects including drain induced barrier lowering and threshold voltage roll-off (ΔVth) are described and their relationship with Φm is given.|
|Source Title:||International Journal of Electronics|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Jan 12, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.