Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/81745
Title: Simulation of 0.1μm hot carrier effect suppressed grooved gate MOSFET
Authors: Sreelal, S.
Lau, C.K.
Samudra, G.S. 
Issue Date: 1999
Source: Sreelal, S.,Lau, C.K.,Samudra, G.S. (1999). Simulation of 0.1μm hot carrier effect suppressed grooved gate MOSFET. International Symposium on IC Technology, Systems and Applications 8 : 490-493. ScholarBank@NUS Repository.
Abstract: A 0.1 μm grooved gate MOSFET has been designed and simulated for its electrical characteristics using two dimensional process and device simulators. A conventional planar device is also simulated to get a reference for comparison of major electrical parameters. It is found that the grooved gate device exhibits high immunity to short channel effects such as hot carrier effects due to impact ionisation and drain induced barrier lowering while at the same time maintaining the major electrical performance parameter values of the planar device. A major handicap of the grooved gate device is its significantly higher values of parasitic capacitances, Cgs and Cgd when compared to the planar device. This degradation is quantified and methods are suggested to overcome this.
Source Title: International Symposium on IC Technology, Systems and Applications
URI: http://scholarbank.nus.edu.sg/handle/10635/81745
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