Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/81583
Title: New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
Authors: Jie, B.B.
Li, M.F. 
Chim, W.K. 
Chan, D.S.H. 
Lo, K.F.
Issue Date: 1999
Citation: Jie, B.B.,Li, M.F.,Chim, W.K.,Chan, D.S.H.,Lo, K.F. (1999). New DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA : 89-93. ScholarBank@NUS Repository.
Abstract: A direct-current voltage-voltage (DCVV) technique for the measurement of stress-generated interface traps in sub-micron metal-oxide-semiconductor transistors (MOSTs) is demonstrated. This method uses the source-bulk-drain of a sub-micron MOST as an effective lateral bipolar transistor when the channel region is out of inversion under the control of the gate voltage Vgb. The emitter injects the minority carriers into the base region and the collector is open. The Vcb versus Vgb spectrum can be explained quantitatively using the extended Ebers-Moll equations and interface trap Shockley-Read-Hall (SRH) recombination. A single effective interface trap at the source or drain side could be detected, and interface traps at the source side can be separated from those at the drain side by the new method.
Source Title: Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
URI: http://scholarbank.nus.edu.sg/handle/10635/81583
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