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|Title:||Investigation of Performance Limits of Germanium Double-Gated MOSFETs|
|Source:||Low, T.,Hou, Y.T.,Li, M.F.,Zhu, C.,Chin, A.,Samudra, G.,Chan, L.,Kwong, D.-L. (2003). Investigation of Performance Limits of Germanium Double-Gated MOSFETs. Technical Digest - International Electron Devices Meeting : 691-694. ScholarBank@NUS Repository.|
|Abstract:||The performance limits and engineering issues of ultra-thin body (UTB) double gated (DG) Ge channel n-MOSFETs are examined in this paper. The non-equilibrium Green's Function (NEGF) approach, including both L and Δ conduction valleys, is employed for source to drain current, while the improved WKB tunneling is employed for substrate to drain (band-to-band BTB) and gate to channel current. All possible Ge surfaces and channel orientations are explored. In terms of drive current I ON, highly anisotropic Ge〈110〉 channel exhibits highest I ON which increases with body thickness scaling; Ge〈100〉 exhibits similar ballistic limit as Si〈100〉 due to increasing Δ valley carrier dominance at UTB regime; Ge〈111〉exhibits higher ballistic limit but decrease at UTB regime due to the small density-of-states mass of L valley. Sub-threshold slope is worse for Ge〈110〉 and Ge〈111〉 as channel length is scaled down. In terms of standby current I OFF and gate leakage I G for low standby power (LSTP) devices, BTB tunneling is large due to the small energy gap of Ge. This imposes a limit on maximum tolerable supply voltage (of which Ge〈111〉 is worst and Ge〈100〉 is best) thus requiring low voltage operation. Body scaling is effective in suppressing BTB tunneling, since carrier quantization causes effective energy gap widening. The low voltage requirement demands small EOT for minimal oxide voltage drop. However, gate leakage will impose a limit for further EOT scaling, of which Ge 〈110〉 is worst and Ge〈111〉 is best. Our results conclude that in addition to lower power supply voltage advantage, the engineered Ge〈110〉 devices with suppressed BTB and gate leakages can achieve better intrinsic delay to OFF power ratio than Si〈100〉 devices.|
|Source Title:||Technical Digest - International Electron Devices Meeting|
|Appears in Collections:||Staff Publications|
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