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|Title:||Simulation of logarithmic time dependence of hot carrier degradation in PMOSFETs|
|Authors:||Ling, C.H. |
|Citation:||Ling, C.H., Samudra, G.S., Seah, B.P. (1995-12). Simulation of logarithmic time dependence of hot carrier degradation in PMOSFETs. Semiconductor Science and Technology 10 (12) : 1659-1666. ScholarBank@NUS Repository.|
|Abstract:||The time dependence of hot carrier degradation in PMOSFETs is simulated on a 2D device simulator, MEDICI. The degradation is modelled by a spatially uniform negative fixed charge, introduced at the oxide-silicon interface. The effect on the device drain current, threshold voltage and transconductance is studied as a function of the extent and magnitude of the fixed charge. The extent of the fixed charge is identified with the drain extension due to the inversion, by the fixed charge, of part of the channel adjacent to the drain junction. The drain extension is experimentally determined from the gate-to-drain capacitance, whose stress time dependence therefore gives an indirect time dependence for the degradation of other device parameters. Simulation results show a logarithmic time dependence of degradation in a number of device parameters, confirming earlier experimental observations. Simulation of the electron injection current reveals two peaks, the first one near the drain junction and the second one near the edge of the degradation region. The second peak is considerably weaker and accounts for the progressively longer time needed to create additional degradation.|
|Source Title:||Semiconductor Science and Technology|
|Appears in Collections:||Staff Publications|
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