Please use this identifier to cite or link to this item:
|Title:||Scaling Parameter Dependent Drain Induced Barrier Lowering Effect in Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor|
|Authors:||Samudra, G. |
|Citation:||Samudra, G.,Rajendran, K. (1999-04-01). Scaling Parameter Dependent Drain Induced Barrier Lowering Effect in Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers 38 (4 PART 2) : 349-352. ScholarBank@NUS Repository.|
|Abstract:||A simple model equation to study the effect of drain induced barrier lowering (DIBL) parameters on device performance for a double-gate (DG) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is proposed. This model equation is used to study the influence of various device parameters on the DIBL effect. The main conclusions drawn from the present study are that: (1) two different approaches for determining the DIBL parameter lead to the same model equation and (2) it is easier to calculate the DIBL parameter rather than extract it from the I-V plots. This model is also easy to implement in a circuit simulator. It is found that the DIBL parameter is almost inversely proportional to the channel length and directly proportional to the gate oxide and silicon thickness. It is shown that a DIBL parameter of less than 0.1 down to a gate length of 0.1 μm is possible at lower Si thicknesses.|
|Source Title:||Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Apr 20, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.