Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2002.1013271
Title: Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs
Authors: Yu, H. 
Hou, Y.-T. 
Li, M.-F. 
Kwong, D.-L.
Keywords: Hole tunneling current
MOSFET
NO stack
Scaling limits
Silicon oxynitrides
Ultrathin gate dielectrics
Issue Date: Jul-2002
Citation: Yu, H., Hou, Y.-T., Li, M.-F., Kwong, D.-L. (2002-07). Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs. IEEE Transactions on Electron Devices 49 (7) : 1158-1164. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2002.1013271
Abstract: The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG| < 2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT = 12 Å if the maximum allowed gate leakage current is 1 A/cm 2 and EOT = 9 Å if the maximum allowed gate leakage current is 100 A/cm 2.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/80633
ISSN: 00189383
DOI: 10.1109/TED.2002.1013271
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