Please use this identifier to cite or link to this item:
|Title:||Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET|
|Authors:||Cheng, Z.-Y. |
|Citation:||Cheng, Z.-Y., Ling, C.H. (2001-02). Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET. IEEE Transactions on Electron Devices 48 (2) : 388-391. ScholarBank@NUS Repository.|
|Abstract:||A gate-channel capacitance minimum occurs in the capacitance-voltage (C-V) curve of a fully-depleted SOI MOSFET, when the front silicon surface is biased into accumulation while the back surface is maintained in strong inversion. This observation is explained in terms of a model based on the depletion width of the silicon film, taking into account the small accumulation and inversion layer thickness. A simple method is proposed to determine the flat-band potential in the SOI MOSFET.|
|Source Title:||IEEE Transactions on Electron Devices|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Feb 27, 2018
WEB OF SCIENCETM
checked on Apr 30, 2018
checked on May 11, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.