Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/80330
Title: Composite step-graded collector of InP/InGaAs/lnP DHBT for minimised carrier blocking
Authors: Chor, E.F. 
Peng, C.J. 
Keywords: Heterojunction bipolar transistors
Semiconductor devices
Issue Date: 18-Jul-1996
Source: Chor, E.F.,Peng, C.J. (1996-07-18). Composite step-graded collector of InP/InGaAs/lnP DHBT for minimised carrier blocking. Electronics Letters 32 (15) : 1409-1410. ScholarBank@NUS Repository.
Abstract: A composite step-graded collector of InP/InGaAs/InP DHBT has been investigated for minimised carrier blocking. The optimised collector has the following sub-layers: a 100Å n- InGaAs layer; three 200Å n- InGaAsP layers; and a 100Å, n = 3 × 1017cm-3 InP layer, and the rest are n- InP. The InGaAsP layers should be chosen to give approximately equal band offset at the heterointerfaces.
Source Title: Electronics Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/80330
ISSN: 00135194
Appears in Collections:Staff Publications

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