Please use this identifier to cite or link to this item: https://doi.org/10.1109/16.658824
Title: A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's
Authors: Ang, D.S. 
Ling, C.H. 
Issue Date: 1998
Source: Ang, D.S., Ling, C.H. (1998). A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET's. IEEE Transactions on Electron Devices 45 (1) : 149-159. ScholarBank@NUS Repository. https://doi.org/10.1109/16.658824
Abstract: A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFET's is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage Vd, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress Vd's, along the stress time axis, until the characteristics merge into a single curve. Index Terms - Charge pumping current, gate-to-drain capacitance, lifetime prediction, MOSFET's, self-limiting hot-carrier degradation, unified model. © 1998 IEEE.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/80284
ISSN: 00189383
DOI: 10.1109/16.658824
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