Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASPDAC.2013.6509688
Title: Shared cache aware task mapping for WCRT minimization
Authors: Ding, H.
Liang, Y.
Mitra, T. 
Issue Date: 2013
Citation: Ding, H.,Liang, Y.,Mitra, T. (2013). Shared cache aware task mapping for WCRT minimization. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 735-740. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2013.6509688
Abstract: The Worst-Case Response Time (WCRT) of multi-tasking applications running on multi-cores is an important metric for real-time embedded systems. The WCRT is determined by the mapping of the tasks to the cores (which determines load balancing) and the Worst-Case Execution Time (WCET) of the tasks. However, the WCET of a task is also influenced by the conflicts in the shared cache from concurrently executing tasks on other cores in a multi-core system. In other words, the mapping of the tasks to the cores indirectly influences the WCET of the tasks, which in turn impacts the WCRT of the entire application. Thus the mapping of the tasks to the cores should simultaneously maximize workload balance and minimize shared cache interference. We propose an integer-linear programming (ILP) formulation to achieve this objective. Experimental evaluation shows that shared cache aware task mapping achieves on an average 25% and 33% WCRT reduction for real-life and synthetic applications, respectively, compared to traditional approach that is agnostic to shared cache conflicts and solely focuses on load balancing. © 2013 IEEE.
Source Title: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
URI: http://scholarbank.nus.edu.sg/handle/10635/78350
ISBN: 9781467330299
DOI: 10.1109/ASPDAC.2013.6509688
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