Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICECCS.2012.29
Title: Parameter synthesis for hierarchical concurrent real-time systems
Authors: Andre, E.
Liu, Y. 
Sun, J.
Dong, J.-S. 
Keywords: CSP
model checking
parametric timed verification
refinement
robustness
Issue Date: 2012
Citation: Andre, E., Liu, Y., Sun, J., Dong, J.-S. (2012). Parameter synthesis for hierarchical concurrent real-time systems. Proceedings - 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems, ICECCS 2012 : 253-262. ScholarBank@NUS Repository. https://doi.org/10.1109/ICECCS.2012.29
Abstract: Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is hence interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesize a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed CSP, a language capable of specifying hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present an algorithm for efficient parameter synthesis that behaves well in practice. © 2012 C.E.S.A.M.E.S.
Source Title: Proceedings - 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems, ICECCS 2012
URI: http://scholarbank.nus.edu.sg/handle/10635/78278
ISBN: 9782954181004
DOI: 10.1109/ICECCS.2012.29
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