Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSI-SoC.2013.6673275
Title: Implementation of core coalition on FPGAs
Authors: Mysur, K.T.
Pricopi, M.
Marconi, T.
Mitra, T. 
Issue Date: 2013
Source: Mysur, K.T.,Pricopi, M.,Marconi, T.,Mitra, T. (2013). Implementation of core coalition on FPGAs. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC : 198-203. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSI-SoC.2013.6673275
Abstract: Embedded systems increasingly need to support dynamic and diverse application landscape. In response, performance asymmetric multi-cores, comprising of identical instruction-set architecture but micro-Architecturally distinct set of simple and complex cores, have emerged as an attractive alternative to accommodate software diversity. Dynamic heterogeneous multi-core architectures take this concept forward by allowing on-demand formation of virtual asymmetric multi-cores through coalition of physically symmetric simple cores and thus adjust better to workload variation at runtime. In this paper, we present the first hardware implementation of a core coalition architecture and synthesize its functional prototype on FPGAs. © 2013 IEEE.
Source Title: IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
URI: http://scholarbank.nus.edu.sg/handle/10635/78181
ISBN: 9781479905249
ISSN: 23248440
DOI: 10.1109/VLSI-SoC.2013.6673275
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

Page view(s)

34
checked on Feb 24, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.