Please use this identifier to cite or link to this item: https://doi.org/10.1145/2463585.2463592
Title: On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
Authors: Chen, Y.
Wong, W.-F. 
Li, H.
Koh, C.-K.
Zhang, Y.
Wen, W.
Keywords: Cache
Memories
MLC
Spintronic
STT-RAM
Issue Date: 2013
Citation: Chen, Y., Wong, W.-F., Li, H., Koh, C.-K., Zhang, Y., Wen, W. (2013). On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM Journal on Emerging Technologies in Computing Systems 9 (2) : -. ScholarBank@NUS Repository. https://doi.org/10.1145/2463585.2463592
Abstract: It has been predicted that a processor's caches could occupy as much as 90% of chip area a few technology nodes from the current ones. In this article, we investigate the use of multilevel spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. We start with examining the access (read and write) scheme for multilevel cell (MLC) STT-RAM from a circuit design perspective, detailing the read and write circuits. Compared to traditional SRAM caches, a multilevel cell (MLC) STT-RAM cache design is denser, fast, and requires less energy. However, a number of critical architecture-level issues remain to be solved before MLC STT-RAM technology can be deployed in processor caches. We shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. In particular, the latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80× on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is proposed. The impacts of process variations of the MLC STT-RAM cell on the robustness of the memory hierarchy is also discussed, together with various enhancement techniques, namely, ECC and design redundancy. © 2013 ACM.
Source Title: ACM Journal on Emerging Technologies in Computing Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/77896
ISSN: 15504832
DOI: 10.1145/2463585.2463592
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

30
checked on Dec 12, 2018

WEB OF SCIENCETM
Citations

7
checked on Dec 12, 2018

Page view(s)

44
checked on Nov 2, 2018

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.