A 0.29 MM2 12-BIT SEGMENTED CURRENT STEERING DAC WITH DIGITALLY ASSISTED ERROR COMPENSATION GROUPING

Abstract

Continuous transistor gate length shrinking has introduced additional design challenges because of reduced voltage headroom and device gain. Digitally-assisted analog/RF circuit design has proved an effective workaround resulting in an increased demand for area-efficient high resolution digital-to-analog converters (DAC) for digital correction application. To address this increased demand, a 12-bit current-steering DAC is presented. Incorporated in the DAC is a statistical grouping calibration technique where small unit current cells with similar but opposite variations are combined to form MSB current cells with smaller variations. While statistical grouping method is not new, this work provides a solution practical for large arrays of elements and focuses on the physical implementation. An offset insensitive calibration method is also proposed to improve the performance. Overall DAC active area is 0.29mm2 with INL of ¿0.7LSB, clearly demonstrating an improvement in current cells matching. The prototype consumes 12 mW at 50 MS/s.