Please use this identifier to cite or link to this item: https://doi.org/10.1109/EPTC.2007.4469679
Title: Structural design and optimization of 65nm Cu/low-k flipchip package
Authors: Ong, J.
Zhang, X.
Kripesh, V.
Lim, Y.K.
Yeo, D.
Chan, K.C.
Tan, J.B.
Hsia, L.C.
Sohn, D.K.
Tay, A. 
Issue Date: 2007
Source: Ong, J., Zhang, X., Kripesh, V., Lim, Y.K., Yeo, D., Chan, K.C., Tan, J.B., Hsia, L.C., Sohn, D.K., Tay, A. (2007). Structural design and optimization of 65nm Cu/low-k flipchip package. Proceedings of the Electronic Packaging Technology Conference, EPTC : 488-492. ScholarBank@NUS Repository. https://doi.org/10.1109/EPTC.2007.4469679
Abstract: The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Very low modulus underfills must also be avoided because low modulus underfills transfer too much stress to the bumps which result in bump cracking in TC testing. A 2D plane strain analysis was performed to investigate the reliability of Chartered's C65nm 21×21mm 9metal Cu/ low-k, chips with 150um interconnect pitch in a FCBGA package. A series of parametric studies are performed by using Polymer Encapsulated Dicing Lane Technology (PEDL) to reduce 1 layer of FSG, variation of Cu post height, die thickness, substrate thickness, and underfill selection. The results obtained from the reduction of the stress in the low-k structure and the inelastic energy in the solder bumps modeling is useful to formulate design guidelines for packaging of large dies. ©2007 IEEE.
Source Title: Proceedings of the Electronic Packaging Technology Conference, EPTC
URI: http://scholarbank.nus.edu.sg/handle/10635/73876
ISBN: 1424413249
DOI: 10.1109/EPTC.2007.4469679
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