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|Title:||Simulation-based design optimization of solder joint reliability of wafer level copper column interconnects|
|Citation:||Wei, S.,Tay, A.A.O.,Vedantam, S. (2005). Simulation-based design optimization of solder joint reliability of wafer level copper column interconnects. Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005 2 : 444-450. ScholarBank@NUS Repository.|
|Abstract:||This paper describes a study of solder joint reliability of a copper column (CuC) interconnect scheme in wafer level packages using a simulation-based design optimization methodology to investigate the effects of various design parameters on the solder joint thermc-mechanical reliability and to find the optimal parameter settings. Design of experiments (DoE), surrogate modeling and numerical optimization techniques, together with computer simulation have been integrated in this approach. Four design parameters are involved in this study, namely the chip thickness, substrate thickness, substrate CTE, and CuC height. A full factorial DoE method is adopted to prescribe the required simulation runs. The incremental equivalent plastic strain will serve as the indicator of solder joint thermo-mechanical reliability By applying this simulation-based design optimization approach, the effects of various parameters are identified and an optimal parameter setting is determined © 2005 IEEE.|
|Source Title:||Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005|
|Appears in Collections:||Staff Publications|
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