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Title: Board level drop test reliability of IC packages
Authors: Chai, T.C.
Quek, S.
Hnin, W.Y.
Wong, E.H.
Chia, J.
Wang, Y.Y.
Tan, Y.M.
Lim, C.T. 
Issue Date: 2005
Source: Chai, T.C.,Quek, S.,Hnin, W.Y.,Wong, E.H.,Chia, J.,Wang, Y.Y.,Tan, Y.M.,Lim, C.T. (2005). Board level drop test reliability of IC packages. Proceedings - Electronic Components and Technology Conference 1 : 630-636. ScholarBank@NUS Repository.
Abstract: This paper discusses the effect of board design, the failure mechanism and the board level drop impact performance of two types of common IC packages for hand held electronic product applications namely QFN and CSP, when subjected to the JESD22-B111 test methodology. A method to design test board using low cost 2-layer FR4 material instead of more expensive buildup technologies for board level drop impact test have been developed. Finite Element Analysis (FEA) of the stress and strain fields during drop impact of the CSP and QFN were performed and verified experimentally. In addition, a cyclic constrained bend test has shown good feasibility to be considered as a simpler alternative assessment of solder joint performance under high strain rate loading. © 2005 IEEE.
Source Title: Proceedings - Electronic Components and Technology Conference
ISSN: 05695503
Appears in Collections:Staff Publications

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