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|Title:||Analytical solutions for interconnect stress in board level drop impact|
|Citation:||Wong, E.H., Mai, Y.-W., Seah, S.K.W., Lim, K.M., Lim, T.B. (2006). Analytical solutions for interconnect stress in board level drop impact. Proceedings - Electronic Components and Technology Conference 2006 : 1808-1815. ScholarBank@NUS Repository. https://doi.org/10.1109/ECTC.2006.1645905|
|Abstract:||Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test. ©2006 IEEE.|
|Source Title:||Proceedings - Electronic Components and Technology Conference|
|Appears in Collections:||Staff Publications|
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