Please use this identifier to cite or link to this item:
|Title:||A numerical study of fatigue life of copper column interconnections in wafer level packages|
|Source:||Sun, W.,Tay, A.A.O.,Vedantam, S. (2004). A numerical study of fatigue life of copper column interconnections in wafer level packages. Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004 : 318-323. ScholarBank@NUS Repository.|
|Abstract:||A Copper Column (CuC) interconnect technology is proposed in the Nano Wafer Level Packaging Program as a chip-to-substrate interconnect solution for 20mm by 20mm package with 100μm pitch. Currently thermo-mechanical reliability of solder joint continues to be a major concern due to the CTE (coefficient of thermal expansion) mismatch between chip and substrate A FEA (finite element analysis) is carried out to estimate the fatigue life of the (critical) outermost corner CuC interconnect under thermal cycling. The commercial FEA software ABAQUS is used. Since a 3D finite element model constructed using 3D solid elements requires prohibitive computational resources, a macro-micro modeling approach which is feasible for handling simulation of large packages is used. This modified approach uses a global shell-and-beam model. By using shell-to-solid submodeling technique, a finely meshed submodel of the critical CuC interconnect can be analyzed. Maximum inelastic shear strain range is then extracted to estimate the solder joint fatigue life based on Solomon's correlation. In the current study, three CuCs with different heights are investigated. Fatigue lives of those three CuC interconnects are estimated and failure sites identified. © 2004 IEEE.|
|Source Title:||Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 9, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.