Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/72990
Title: VLSI circuits for decomposing binary integers into signed power-of-two terms
Authors: Yong, Ching Lim 
Liu, Bede
Evans, Joseph B.
Issue Date: 1990
Source: Yong, Ching Lim,Liu, Bede,Evans, Joseph B. (1990). VLSI circuits for decomposing binary integers into signed power-of-two terms. Proceedings - IEEE International Symposium on Circuits and Systems 3 : 2304-2307. ScholarBank@NUS Repository.
Abstract: If the coefficients of a digital filter are approximated by the sum of signed power-of-two terms, there will be a significant reduction in the area used and an improvement in the speed of custom implementations at the expense of a slight frequency-response deterioration. The authors present two circuits for extracting from a given integer a prescribed number of signed power-of-two terms whose sum is the closest approximation to that given integer. One of these circuits is bit-serial and the other is bit-parallel. Example layouts in a CMOS process are given.
Source Title: Proceedings - IEEE International Symposium on Circuits and Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/72990
ISSN: 02714310
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

Page view(s)

53
checked on Dec 16, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.