Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/72753
DC Field | Value | |
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dc.title | Modelling of the "Gated-diode" configuration in bulk MOSFET's | |
dc.contributor.author | Yip, A. | |
dc.contributor.author | Yeow, Y.T. | |
dc.contributor.author | Samudra, G.S. | |
dc.contributor.author | Ling, C.H. | |
dc.date.accessioned | 2014-06-19T05:11:37Z | |
dc.date.available | 2014-06-19T05:11:37Z | |
dc.date.issued | 2000 | |
dc.identifier.citation | Yip, A.,Yeow, Y.T.,Samudra, G.S.,Ling, C.H. (2000). Modelling of the "Gated-diode" configuration in bulk MOSFET's. 2000 International Conference on Modeling and Simulation of Microsystems - MSM 2000 : 360-363. ScholarBank@NUS Repository. | |
dc.identifier.isbn | 0966613570 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/72753 | |
dc.description.abstract | A study of the "gated-diode" configuration in MOSFET's for characterising hot-carrier degradation by employing 2-D simulations is presented in this paper. We use both process and device simulations to understand operational sensitivity of this technique. The parameters involved in the gated-diode measurement like recombination processes and carrier concentrations, which are not available from experiments, will be discussed. The interface trap distribution across the bandgap and spatial distribution are also explored here. In addition, the gated-diode measurement method is modelled with specific task of determining interface state density. | |
dc.source | Scopus | |
dc.subject | Gated-diode | |
dc.subject | Hot-carrier effects | |
dc.subject | Interface traps | |
dc.subject | MOSFET | |
dc.subject | Simulation | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.description.sourcetitle | 2000 International Conference on Modeling and Simulation of Microsystems - MSM 2000 | |
dc.description.page | 360-363 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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