Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/72480
Title: Analysis and design of power factor correction using half bridge boost topology
Authors: Srinivasan, Ramesh
Oruganti, Ramesh 
Issue Date: 1997
Source: Srinivasan, Ramesh,Oruganti, Ramesh (1997). Analysis and design of power factor correction using half bridge boost topology. Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC 1 : 489-499. ScholarBank@NUS Repository.
Abstract: A single phase, high efficiency, and near-unity power factor half-bridge boost converter circuit, which has been proposed earlier by other researchers, is presented with detailed analysis. Though this converter is capable of operating under variable power factor, the focus of this paper is in achieving unity power factor operation only. The efficiency of this circuit is high because there is only one series semiconductor on-state voltage drop at any instant. The existence of an imbalance in the voltages of the two dc link capacitors, which was noted before, is confirmed here. The cause of the imbalance is analyzed using appropriate models, and a control method to eliminate it is discussed in detail. Analysis and design considerations for the power circuit using the fixed band hysteresis current control technique are provided. The analytical results are verified through simulation using switched and averaged circuit models of the scheme and also through experimental work. At 90V ac input and 300W, 300V output, the experimental prototype demonstrates an efficiency of 96% and a power factor of 0.998. This converter, with its relatively high dc output voltage, is well suited for 110V utility supply system. A circuit modification for universal input voltage range operation is also suggested.
Source Title: Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
URI: http://scholarbank.nus.edu.sg/handle/10635/72480
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