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|Title:||Dispatching heuristic for wafer fabrication|
|Authors:||Lee, L.H. |
|Citation:||Lee, L.H.,Tang, L.C.,Chan, S.C. (2001). Dispatching heuristic for wafer fabrication. Winter Simulation Conference Proceedings 2 : 1215-1219. ScholarBank@NUS Repository.|
|Abstract:||As the semiconductor industry moves into the next millenium, companies increasingly will be faced with production obstacles that impede their ability to remain competitive. Effective equipment and line management planning will increasingly be required to maximize profitability while maintaining the flexibility to keep pace with rapidly changing manufacturing environment. In this paper, the authors present a two-bottleneck machines center model for wafer operations analysis. A new dispatching rule Balance Work Content, BWC, is introduced. This is a selective dispatching rule whereby it attempts to maximize the utilization of bottleneck machine. A systematic approach to assessing the impact of BWC is presented. Extensive simulation runs on both the deterministic and stochastic models developed shows its supremacy over conventional approaches of FIFO and SPT.|
|Source Title:||Winter Simulation Conference Proceedings|
|Appears in Collections:||Staff Publications|
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