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|Title:||TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs|
|Source:||Haque, M.S.,Kumar, A.,Ha, Y.,Wu, Q.,Luo, S. (2013). TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 320-325. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2013.6509615|
|Abstract:||Hitherto discovered approaches analyze the execution time of a real-time application on all the possible cache hierarchy setups to find the application specific optimal two-level inclusive data cache hierarchy to reduce cost, space and energy consumption while satisfying the time deadline in real-time Multi-Processor Systems on Chip (MPSoC). These brute-force like approaches can take years to complete. Alternatively, application's memory access trace driven crude estimation methods can find a cache hierarchy quickly by compromising the accuracy of results. In this article, for the first time, we propose a fast and accurate application's trace driven approach to find the optimal real-time application specific two-level inclusive data cache hierarchy. Our proposed approach 'TRISHUL' predicts the optimal cache hierarchy performance first and then utilizes that information to find the optimal cache hierarchy quickly. TRISHUL can suggest a cache hierarchy, which has up to 128 times smaller size, up to 7 times faster compared to the suggestion of the state-of-the-art crude trace driven two-level inclusive cache hierarchy selection approach for the application traces analyzed. © 2013 IEEE.|
|Source Title:||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|
|Appears in Collections:||Staff Publications|
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