Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/71958
Title: Test bench modeling and characterization for fine pitch wafer level packaged devices
Authors: Jayabalan, J. 
Mihai, R.D.
Tan, J.P.H.
Iyer, M.K.
Leong, O.B.
Seng, L.M. 
Keywords: Fine pitch
Interconnect modeling
Multi-gigahertz test
Wafer level package
Issue Date: 2004
Source: Jayabalan, J.,Mihai, R.D.,Tan, J.P.H.,Iyer, M.K.,Leong, O.B.,Seng, L.M. (2004). Test bench modeling and characterization for fine pitch wafer level packaged devices. Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004 : 502-505. ScholarBank@NUS Repository.
Abstract: This paper describes an interposer hardware for testing fine pitch wafer level packaged devices. It is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG probes. All the components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB and trampoline mesh have been modeled. A sample chip, without bumps on the pads, has also been measured. The measurement and models demonstrate that the test socket performs at 5 GHz with an insertion loss of about 3dB. © 2004 IEEE.
Source Title: Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004
URI: http://scholarbank.nus.edu.sg/handle/10635/71958
ISBN: 0780388216
Appears in Collections:Staff Publications

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