Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASPDAC.2008.4483935
Title: Statistical noise margin estimation for sub-threshold combinational circuits
Authors: Pu, Y.
De Gyvez, J.P.
Corporaal, H.
Ha, Y. 
Issue Date: 2008
Source: Pu, Y.,De Gyvez, J.P.,Corporaal, H.,Ha, Y. (2008). Statistical noise margin estimation for sub-threshold combinational circuits. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 176-179. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2008.4483935
Abstract: The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new equivalent resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits. ©2008 IEEE.
Source Title: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
URI: http://scholarbank.nus.edu.sg/handle/10635/71864
ISBN: 9781424419227
DOI: 10.1109/ASPDAC.2008.4483935
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