Statistical noise margin estimation for sub-threshold combinational circuits
Pu, Y. De Gyvez, J.P. Corporaal, H. Ha, Y.
Pu, Y.
De Gyvez, J.P.
Corporaal, H.
Citations
Altmetric:
Alternative Title
Abstract
The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new equivalent resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits. ©2008 IEEE.
Keywords
Source Title
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Publisher
Series/Report No.
Collections
Rights
Date
2008
DOI
10.1109/ASPDAC.2008.4483935
Type
Conference Paper