Reducing tag activities for power efficiency in I-cache memory

Abstract

As the clock frequency and cache size increase in modern microprocessors, the excessive power consumption in cache memory attracts more and more attention and research interest. This paper proposes a software and hardware co-design method to reduce the tag activities for power efficiency with little performance penalty. Using the run-time profile data, we trace the object code dynamically and extract the loops, subroutines, branches etc., and predict the point of time when tag checks are not needed for instruction fetching from I-cache memory. With support from simple logic circuits, the tags could be disabled and enabled timely to save power. The overhead of power consumption in the tag controller is negligible due to its simplicity and the low frequency of tag switches. Our experimental results using a subset of SPEC 2000 benchmarks showed that this strategy could reduce 20.6% of energy consumption in a 16K I-cache on average with only 0.13% of performance loss. © 2006 IEEE.