Please use this identifier to cite or link to this item: https://doi.org/10.1109/PESC.2001.954439
Title: Poly Flanked VDMOS (PFVDMOS): A superior technology for superjunction devices
Authors: Gan, K.P.
Liang, Y.C. 
Samudra, G.S. 
Xu, S.M.
Yong, L.
Keywords: Superjunction MOS structure
VDMOS
Issue Date: 2001
Source: Gan, K.P.,Liang, Y.C.,Samudra, G.S.,Xu, S.M.,Yong, L. (2001). Poly Flanked VDMOS (PFVDMOS): A superior technology for superjunction devices. PESC Record - IEEE Annual Power Electronics Specialists Conference 4 : 2156-2159. ScholarBank@NUS Repository. https://doi.org/10.1109/PESC.2001.954439
Abstract: A novel VDMOS structure, named Poly Flanked VDMOS (PFVDMOS), is proposed for the first time to provide a better performance and process technology for superjunction MOSFET devices. The structure contains a thin oxide barrier to eliminate the existing p-n lateral inter-diffusion problem, thus both the n-epi and p poly column widths can be reduced to a minimum. This reduction in column width enables the device to have a much higher n-epi doping concentration. And, in a sense, it leads to an optimal reduction in on-state resistance comparing to other existing structures for the same voltage rating.
Source Title: PESC Record - IEEE Annual Power Electronics Specialists Conference
URI: http://scholarbank.nus.edu.sg/handle/10635/71466
ISBN: 0780370678
ISSN: 02759306
DOI: 10.1109/PESC.2001.954439
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