Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPT.2012.6412111
Title: Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs
Authors: Wang, C.
Li, X.
Zhou, X.
Ha, Y. 
Issue Date: 2012
Source: Wang, C.,Li, X.,Zhou, X.,Ha, Y. (2012). Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs. FPT 2012 - 2012 International Conference on Field-Programmable Technology : 53-56. ScholarBank@NUS Repository. https://doi.org/10.1109/FPT.2012.6412111
Abstract: Reconfigurable hybrid multi-processor systems-on-chips (MPSoCs) are very powerful computing platforms. However, it has been quite challenging to schedule and map tasks to different function units of the MPSoCs, especially for tasks with inter-task dependencies. This paper introduces a parallel dataflow execution support, called ReArc, for the FPGA based reconfigurable hybrid MPSoCs. It constructs a hierarchical model for the high level programming with a parallel execution flow and dynamic reconfigurations. A prototype has been built on a Xilinx FPGA with a state-of-the-art software-hardware co-design paradigm. Experimental results demonstrate that ReArc could significantly facilitate researchers to construct a high-level, application oriented FPGA implementation with acceptable hardware utilizations and reconfiguration overheads. © 2012 IEEE.
Source Title: FPT 2012 - 2012 International Conference on Field-Programmable Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/71356
ISBN: 9781467328449
DOI: 10.1109/FPT.2012.6412111
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