Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2008.4588551
Title: Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance
Authors: Lee, R.T.-P. 
Koh, A.T.-Y.
Fang, W.-W.
Tan, K.-M.
Lim, A.E.-J.
Liow, T.-Y.
Chow, S.-Y.
Yong, A.M.
Hoong, S.W.
Lo, G.-Q.
Samudra, G.S. 
Chi, D.-Z.
Yeo, Y.-C. 
Issue Date: 2008
Source: Lee, R.T.-P.,Koh, A.T.-Y.,Fang, W.-W.,Tan, K.-M.,Lim, A.E.-J.,Liow, T.-Y.,Chow, S.-Y.,Yong, A.M.,Hoong, S.W.,Lo, G.-Q.,Samudra, G.S.,Chi, D.-Z.,Yeo, Y.-C. (2008). Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance. Digest of Technical Papers - Symposium on VLSI Technology : 28-29. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2008.4588551
Abstract: We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20 % reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement. © 2008 IEEE.
Source Title: Digest of Technical Papers - Symposium on VLSI Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/71171
ISBN: 9781424418053
ISSN: 07431562
DOI: 10.1109/VLSIT.2008.4588551
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