Please use this identifier to cite or link to this item: https://doi.org/10.1145/1367045.1367049
Title: Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
Authors: Kumar, A. 
Fernando, S. 
Ha, Y. 
Mesman, B.
Corporaal, H.
Keywords: Design exploration
FPGA
Multi-application
Multimedia systems
Multiple use-cases
Multiprocessor systems
Synchronous data-flow graphs
Issue Date: 1-Jul-2008
Source: Kumar, A., Fernando, S., Ha, Y., Mesman, B., Corporaal, H. (2008-07-01). Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Transactions on Design Automation of Electronic Systems 13 (3) : -. ScholarBank@NUS Repository. https://doi.org/10.1145/1367045.1367049
Abstract: Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone. In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for. The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications. © 2008 ACM.
Source Title: ACM Transactions on Design Automation of Electronic Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/71065
ISSN: 10844309
DOI: 10.1145/1367045.1367049
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