Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPL.2007.4380631
Title: Multi-processor system-level synthesis for multiple applications on platform FPGA
Authors: Kumar, A. 
Fernando, S. 
Ha, Y. 
Mesman, B.
Corporaal, H.
Issue Date: 2007
Source: Kumar, A., Fernando, S., Ha, Y., Mesman, B., Corporaal, H. (2007). Multi-processor system-level synthesis for multiple applications on platform FPGA. Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL : 92-97. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2007.4380631
Abstract: Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and programming such systems prove to be a major challenge. Most of the current design methodologies rely on creating the design by hand, and are therefore error-prone and time-consuming. This also limits the number of design points that can be explored. While some efforts have been made to automate the flow and raise the abstraction level, these are still limited to single-application designs. In this paper, we present a design methodology to generate and program MPSoC designs in a systematic and automated way for multiple applications. The architecture is automatically inferred from the application specifications, and customized for it. The flow is ideal for fast design space exploration (DSE) in MPSoC systems. We present results of a case study to compute the buffer-throughput trade-offs in real-life applications, H263 and JPEG decoders. The generation of the entire project takes about 100ms, and the whole DSE was completed in 45 minutes, including the FPGA mapping and synthesis. © 2007 IEEE.
Source Title: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
URI: http://scholarbank.nus.edu.sg/handle/10635/71064
ISBN: 1424410606
DOI: 10.1109/FPL.2007.4380631
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