Please use this identifier to cite or link to this item:
https://doi.org/10.1109/FPT.2010.5681427
DC Field | Value | |
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dc.title | Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA | |
dc.contributor.author | Singh, A.K. | |
dc.contributor.author | Kumar, A. | |
dc.contributor.author | Srikanthan, T. | |
dc.contributor.author | Ha, Y. | |
dc.date.accessioned | 2014-06-19T03:17:23Z | |
dc.date.available | 2014-06-19T03:17:23Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Singh, A.K.,Kumar, A.,Srikanthan, T.,Ha, Y. (2010). Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 : 365-368. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/FPT.2010.5681427" target="_blank">https://doi.org/10.1109/FPT.2010.5681427</a> | |
dc.identifier.isbn | 9781424489817 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/70883 | |
dc.description.abstract | Multiprocessor systems-on-chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. These MPSoCs are employing Network-on-Chip (NoC) for reasons of efficiency and scalability. Additionally, these systems need to support run-time reconfiguration of their components to cater to dynamically changing demands of the system. Designing and programming such systems for real-life applications prove to be a major challenge. This paper demonstrates the designing of reconfigurable NoC-based MPSoC and programming it for real-life applications. The NoC is reconfigured at run-time to support different combinations of multiple applications at different times. The platform is verified with a case study executing the parallelized C-codes of a simple producer-consumer and JPEG decoder applications on a NoC-based MPSoC on a Xilinx FPGA. Based on our investigations to map the applications on a 3×3 platform, we show that the NoC reconfiguration overhead is kept at a minimum and the platform utilizes 85% of the total available slices of Virtex-5 FPGA. Moreover, we show that the proposed approach is highly scalable when targeting for large number of applications. © 2010 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/FPT.2010.5681427 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/FPT.2010.5681427 | |
dc.description.sourcetitle | Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 | |
dc.description.page | 365-368 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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