Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.tsf.2005.09.152
Title: Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning
Authors: Bliznetsov, V.
Kumar, R.
Lin, H.
Ang, K.-W.
Yoo, W.J. 
Du, A.
Keywords: Dipole ring magnetron
Hard mask
Photoresist trimming
Sub-50 nm
Issue Date: 10-May-2006
Source: Bliznetsov, V., Kumar, R., Lin, H., Ang, K.-W., Yoo, W.J., Du, A. (2006-05-10). Integrated process of photoresist trimming and dielectric hard mask etching for sub-50 nm gate patterning. Thin Solid Films 504 (1-2) : 117-120. ScholarBank@NUS Repository. https://doi.org/10.1016/j.tsf.2005.09.152
Abstract: Photoresist (PR) trimming for narrowing gate critical dimensions (CD) to sub-50 nm range is a known technique in polysilicon gate CMOS technology. However, the trend to replace polysilicon by a suitable metal such as TaN involves replacement of PR mask by a dielectric hard mask (HM) for providing tight CD and profile control in subsequent TaN etching. We have found that traditional selective etching of dielectrics on top of TaN film poses many challenges. Besides, PR trimming also should be tuned so that PR mask after trimming could match requirements of HM etching. By study and optimization of both PR trimming and HM etching in dipole ring magnetron etcher, we developed a production worthy processes for fabrication of sub-50 nm hard mask used for TaN gate etching in CMOS technology. © 2005 Elsevier B.V. All rights reserved.
Source Title: Thin Solid Films
URI: http://scholarbank.nus.edu.sg/handle/10635/70623
ISSN: 00406090
DOI: 10.1016/j.tsf.2005.09.152
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