Please use this identifier to cite or link to this item:
|Title:||In-situ fault detection of wafer warpage in lithography|
|Authors:||Tay, A. |
|Citation:||Tay, A.,Ho, W.K.,Yap, C.,Wei, C.,Tsai, K.-Y. (2005). In-situ fault detection of wafer warpage in lithography. IFAC Proceedings Volumes (IFAC-PapersOnline) 16 : 67-72. ScholarBank@NUS Repository.|
|Abstract:||Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ fault detection technique for wafer warpage in lithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. in this paper, the use of advanced process control resulted in very small temperature disturbance making it suitable for industrial implementation. More importantly, the sensitivity for detecting warpage is not compromised even though the temperature signal is small. Experimental results demonstrate the feasibility of the approach. Copyright © 2005 IFAC.|
|Source Title:||IFAC Proceedings Volumes (IFAC-PapersOnline)|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Nov 3, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.