Please use this identifier to cite or link to this item: https://doi.org/10.1109/TSM.2004.831536
Title: In situ fault detection of wafer warpage in microlithography
Authors: Ho, W.K. 
Tay, A. 
Zhou, Y.
Yang, K.
Keywords: Fault detection
Microlithography
Temperature measurement
Wafer warpage
Issue Date: Aug-2004
Source: Ho, W.K., Tay, A., Zhou, Y., Yang, K. (2004-08). In situ fault detection of wafer warpage in microlithography. IEEE Transactions on Semiconductor Manufacturing 17 (3) : 402-407. ScholarBank@NUS Repository. https://doi.org/10.1109/TSM.2004.831536
Abstract: Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates.
Source Title: IEEE Transactions on Semiconductor Manufacturing
URI: http://scholarbank.nus.edu.sg/handle/10635/70573
ISSN: 08946507
DOI: 10.1109/TSM.2004.831536
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