Please use this identifier to cite or link to this item: https://doi.org/10.1109/FCCM.2013.32
Title: High speed video processing using fine-grained processing on FPGA platform
Authors: Ang, Z.P.
Kumar, A. 
Ha, Y. 
Keywords: Bit-serial arithmetic
Fine-grained FPGA computing
High speed video processing
Partial reconfiguration
Issue Date: 2013
Source: Ang, Z.P., Kumar, A., Ha, Y. (2013). High speed video processing using fine-grained processing on FPGA platform. Proceedings - 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013 : 85-88. ScholarBank@NUS Repository. https://doi.org/10.1109/FCCM.2013.32
Abstract: This summary paper1 proposes an FPGA-based array processor which performs Laplacian filtering on a 40 by 40 pixel grayscale video. The architecture comprises of bitserial pixel processors interconnected to give a two-dimensional mesh array. This architecture features the novel use of partial reconfiguration which transfers data to and fro the array. Each processor occupies a configurable logic block and achieves a target frame rate of 10000 frames per second, at an operating frequency of 0.31 MHz on the Virtex-6 ML605 Evaluation Kit. The detailed correspondence between the contents of slice lookup tables and the Virtex-6 bitstream format is also documented. © 2013 IEEE.
Source Title: Proceedings - 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013
URI: http://scholarbank.nus.edu.sg/handle/10635/70472
DOI: 10.1109/FCCM.2013.32
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

4
checked on Dec 6, 2017

WEB OF SCIENCETM
Citations

1
checked on Nov 20, 2017

Page view(s)

24
checked on Dec 10, 2017

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.