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Please use this identifier to cite or link to this item: https://doi.org/10.1109/RFIT.2005.1598914
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dc.titleDesign and analysis of a high-speed comparator
dc.contributor.authorJun, G.
dc.contributor.authorYong, L.
dc.contributor.authorBo, S.
dc.date.accessioned2014-06-19T03:04:56Z
dc.date.available2014-06-19T03:04:56Z
dc.date.issued2005
dc.identifier.citationJun, G.,Yong, L.,Bo, S. (2005). Design and analysis of a high-speed comparator. Proceedings - 2005 IEEE International Workshop on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, RFIT 2005 2005 : 215-218. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/RFIT.2005.1598914" target="_blank">https://doi.org/10.1109/RFIT.2005.1598914</a>
dc.identifier.isbn0780393724
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69814
dc.description.abstractThis paper presents the design and analysis of an ultra high-speed bipolar comparator based on master-slave architecture. The comparator can be used for very high speed data converters design. Master-slave structure is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-μm SiGe BiCMOS process, the comparator consumes approximately 70mW with sampling speed of 16GHz and resolvable minimum input voltage of 8mV peak-to-peak.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/RFIT.2005.1598914
dc.sourceScopus
dc.subjectAnalog-to-digital converters
dc.subjectBipolar IC design
dc.subjectFlash ADC design
dc.subjectHigh-speed comparator design
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/RFIT.2005.1598914
dc.description.sourcetitleProceedings - 2005 IEEE International Workshop on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, RFIT 2005
dc.description.volume2005
dc.description.page215-218
dc.identifier.isiutNOT_IN_WOS
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