Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPT.2010.5681443
Title: An area-efficient dynamically reconfigurable spatial division multiplexing Network-on-Chip with static throughput guarantee
Authors: Yang, Z.J.
Kumar, A. 
Ha, Y. 
Keywords: Dynamic reconfiguration
FPGA
Network-on-Chip
Spatial division multiplexing
Throughput guarantee
Issue Date: 2010
Source: Yang, Z.J.,Kumar, A.,Ha, Y. (2010). An area-efficient dynamically reconfigurable spatial division multiplexing Network-on-Chip with static throughput guarantee. Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 : 389-392. ScholarBank@NUS Repository. https://doi.org/10.1109/FPT.2010.5681443
Abstract: With an increasing trend to implement Network-on-Chip (NoC)-based Multi-Processor Systems-on-Chips (MPSoCs), NoCs need to have guaranteed services and be dynamically reconfigurable. Many current NoCs consume too much area and cannot support dynamic reconfiguration. In this paper, we present an area-efficient Spatial Division Multiplexing (SDM)-based NoC. We replaced area consuming 32-bit to M-bit serializers with 32-bit to 1-bit serializers in the network interface and incur almost no loss in performance. We also restrict flexibility in the router to achieve further area reduction. A separate area-efficient control network, with an overhead of 3.9% of the total area of the NoC, is developed to support dynamic reconfiguration. © 2010 IEEE.
Source Title: Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
URI: http://scholarbank.nus.edu.sg/handle/10635/69283
ISBN: 9781424489817
DOI: 10.1109/FPT.2010.5681443
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